Erasable Programmable Read-only Memories (EPROMs), Electrically Erasable Programmable Read-only Memories (E.sup.2 PROMs), and Flash E.sup.2 PROMs (hereafter collectively, PROMs) have several structures which allow them to hold a charge without refresh for extended periods of time. FIG. 1 shows a top view of a PROM array, FIG. 2 shows a cross section along "AA" of FIG. 1, and FIG. 3 shows a cross section along "BB" of FIG. 1. The charge itself is stored on a "floating gate" 10 also referred to as Poly 1 or P1, which is a structure of polycrystalline silicon (hereafter, poly) surrounded on all sides by a layer of oxide 12. Located superjacent and parallel to this P1 structure is another poly structure, the "control gate" 14 or P2. P1 10 and P2 14 act as the two plates of a capacitor. Below the P1 layer are two N+ junctions, one which acts as the transistor source 16 and the other as the drain 18, which are doped into a P-type substrate 20. The portion of the substrate 20 between the source 16 and the drain 18 is the channel 22. The cell functions like an enhancement-type N-channel metal oxide semiconductor field effect transistor (MOSFET) with two gates of poly.
There are structures that make up a PROM array which are common to several transistors in the array. FIG. 1 shows the transistor sources 16, drains 18, digit lines 24, floating gates 10, and control or "word" lines 26 which form control gates 14 as they pass over the floating gates 10. Also shown as a dotted line is the "active area" 28 interspersed with areas of field oxide 30. A single word line 26 is common to all transistors in a single column acting as a control gate 14 for all transistors in the column. When the word line is selected it activates all transistors in the column. The source regions 16, which run parallel with the control lines 26, are common to all transistors in two adjacent columns. Individual transistor drains 18 are common to two transistors in adjacent columns. The digit (or bit) lines 24 are common with the drains 18 of all transistors in a single row.
The voltage potential which must be applied on the control gate to turn on the transistor is much higher in a device storing a charge (for example, storing -5 V) than in a device which does not have a potential stored on P1. To read the content of the floating gate, the source is tied to ground while the drain (by way of its digit line) is tied to a voltage, for example +1 V. A potential somewhere between the low and high potential values of the cell (i.e. the select voltage), for example +5 V, is applied to the control gate. A cell that does not conduct when the select voltage is applied to the control gate has a negative charge stored on P1, while a cell which does not have a negative charge stored on P1 will conduct heavily.
There are many ways to program a PROM. In one technique, a potential such as 12 V, for example, is applied on the control gate. Simultaneously, a voltage pulse, for example 6 V, is applied between source and drain. The large positive potential on the control gate establishes an electric field in the insulating oxide. This electric field generates the so-called "hot electron injection" of the transistor due to the high drain and control gate potentials, and injects the hot electrons into the floating gate. In this way the floating gate is charged, and the charge that accumulates on the floating gate becomes trapped.
Another programming method is by Fowler-Nordheim tunneling. By applying a high potential on the word line and grounding the source and/or the drain, electrons will tunnel through the thin gate oxide to the floating gate. Fowler-Nordheim tunneling is critically determined by the potential between the control gate and the source and/or drain (and therefore the electric field) and the thickness of the gate oxide.
To return the floating gate from a charged state to a state with no charge (erase), the electrons are caused to return to the substrate. In an EPROM, this is accomplished with ultraviolet light which excites the electrons past a certain energy state, thereby allowing them to pass through the oxide and return to the substrate. In an E.sup.2 PROM, this excitation is accomplished with an electrical field, for example by applying 11 V to the source and 0 V to the control gate while the drain is allowed to float. After erase, a device can be reprogrammed by placing a charge on those cells requiring a charge, and the remaining cells are not programmed.
One problem that can occur with floating gate devices is over-erase. Over-erase can occur when an excessive number of electrons stored on the floating gate of a programmed cell are removed, for example during a normal erase procedure. This can occur if the gate oxide under the floating gate is too thin, thereby decreasing the resistance to the flow of electrons through the gate oxide. Other mechanisms for over-erase are not yet known, however over-erase can be unpredictable and can be random from cell to cell. One cause of random over-erase may be the movement of holes through the gate oxide which makes the movement of electrons from the floating gate to the substrate during erase more efficient. Regardless of the cause of the over-erase, an over-erased cell will have a positively charged floating gate which can shift the threshold voltage close to 0.0 V or, in extreme cases, to a negative voltage.
A method of programming a cell which corrects an over-erased cell would be desirable.